The NIRS 3 Four-Wavelength System

Since Animal II demonstrated that Pulse-TDM encoding was a viable technique, a nonimaging point measurement system suitable for performing Near-Infrared Spectroscopy (NIRS) was designed around this technique. The NIRS3 instrument is a time-encoded CW instrument designed for research involving photon migration in both animals and humans, and contains four pairs of optical sources and eight identical optical detectors. The detected signals are demodulated internally and fed in analog form to a panel-mounted connector which is compatible with the PCM-DAS16/16 data acquisition board and interface cable, manufactured by Computer Boards, Inc., Middleboro, MA.

Features and Specifications:

Laser diode sources

Detectors

Detector Channels

System

Safety

Operating Conditions

Circuit Design Approach

The purpose of this instrument is to measure the flux which reaches each detector from up to four different source wavelengths simultaneously. This is achieved using a technique called pulsed time-domain multiplexing, or Pulse-TDM for short, in which each of the four sources is time-interleaved and pulsed at a duty cycle of 12.5%. Thus the detectors see only the flux from one source wavelength at a time. The demodulation circuitry decommutates these pulses and synchronously rectifies them, yielding four analog outputs whose amplitude corresponds to the amount of flux being detected from each of the four source wavelengths.

Each of the eight detectors will generate these four outputs. This means that a total of 8 x 4, or 32 independent analog channels must be made available to the PC Card for data acquisition. Since it was decided to use one 16-input ADC card, the choice was made to multiplex the data into two banks of 16 analog channels each. In order to eliminate ambiguity as to which bank of data is which, one bank will be ground-referenced and the other bank will be referenced to –4.75V. This voltage was chosen to provide a 250mV safety margin above the –5V lower dynamic range limit of the ADC, to handle some voltage drift with time. Synchronization between the ADC sample rate and the analog multiplexer is achieved by dividing down the ADC convert pulse and using this clock to control the multiplexing process.

A timing diagram and a block diagram of the system are shown below. Timing is derived from a crystal clock, and drives both the laser pulsing circuitry and the demodulation circuitry. The optical pulses generated by the lasers are detected by the silicon APD detectors. The electrical signals pass through a variable-gain amplifier and then on to the demodulator.

The clock circuitry was designed to be extremely flexible so that the timing could be varied as needed. Both the modulation clock and the settling delay period are jumper-selectable.

The laser driver circuitry uses a class A design to minimize radiated and conducted EMI at the cost of increased power dissipation. Since this unit was designed to operate in a climate-controlled environment from 120VAC line power, the additional 10 Watts of power consumption was not considered to be a problem.

Each laser can be gated independently. This is achieved by sending an 8-bit serial data word to the unit, using DIO#1 and DIO#2 as normal and inverted clocks, and DIO#3 for the data. Each bit controls one laser, and is loaded as D1 . . . D8. The ordering is shown in the table below:

The laser diode control register settings.

The variable gain amplifier (VGA) consists of two identical series-connected amplifier stages. Analog switches are used to select various feedback resistor combinations to close the loop around the two opamps. Two separate gain stages were chosen to provide a wide (1000 to 1) gain selection range while still allowing the use of standard operational amplifiers with modest gain-bandwidth products. This both reduced cost and minimized the risk of oscillation from excess loop gain at low settings. The additional propagation delay introduced by the second stage is minimal in comparison to the temporal response of the APD, and so it can be safely ignored. Discrete resistor programmed gain (as opposed to logarithmically-variable gain) was selected because it provides very stable and reproducible gain values, each of which can be changed relatively easily in hardware, if desired. Gain stability and repeatability are important for certain optical measurements.

The gain of all eight preamps is controlled by a 32-bit dataword sent in serial fashion, beginning with D1 and ending with D32. DIO#7 and DIO#6 are clock and clock_bar, and DIO#5 is data. Each nybble controls the gain of one preamp. The preamp control register settings are shown in the table below:

Variable-gain preamplifier control register settings.

The gain values were selected to cover as much dynamic range as practical, given the saturation limits of the APD detector modules. The lowest gain setting was set at 1V/V to exploit the maximum 10Vpp output swing available from the APD module. The highest gain setting was chosen to ensure that the noise floor would not be ADC quantization-limited after coaddition of enough samples to reduce the effective noise bandwidth to ~0.1Hz (this represented the combination of temporal averaging down to 3Hz and coaddition of 1000 time-locked recordings). For the APD detectors, the RMS noise over a 100kHz bandwidth was previously measured at 1mV. So compressing this to 0.1Hz yields about 1.2uV of detector noise (flicker noise is being neglected here because it will be reduced both by the avalanche gain and by the modulation process.) The ADC operates over the +/-5V input range, which yields a voltage of 153uV per digital count. It was assumed that the ADC quantization noise floor would be around 1 count (which is about triple the theoretical limit) due to differential nonlinearity and conversion noise. So the noise of the amplified signal must be at least three times this value, about 450uV RMS, to avoid being quantization noise limited. This indicated that a gain of about 400V/V would be sufficient. A 3x gain step was judged to be adequate for DOT measurements, so a maximum gain value of 1000V/V was chosen to provide a convenient gain step sequence: 1, 3.3, 10, 33, etc. up to 1000V/V. Note that, since these gains are determined by discrete resistors, they can be changed to set the gain steps to other values, if needed.

To prevent external flux from debiasing the amplifiers, their inputs are AC-coupled. Since there is no obvious feedback to the user when the APD or the amplifiers are clipping or are saturated by excessive flux, a clipping detection circuit was designed. When the APD output is saturated, the red “DC” overload indicator illuminates. When the amplifier stage begins to clip, the red “AC” overload indicator illuminates.

The demodulator is designed to both demultiplex and demodulate the signals from all four laser wavelengths simultaneously. This is performed with a circuit which functions like a multichannel scaler: during the first of eight time intervals, the first laser wavelength is operating, and the detected signal is fed into the first “bin” (a two-pole RC filter) for averaging. During the second time interval all lasers are off, and this reference signal is averaged in the second “bin.” The third and fourth time intervals are for the second laser wavelength, and so on. The signal and reference bins for each source are then fed to a unity-gain differential amplifier stage which removes any common-mode interference and converts the signal to normal mode (i.e. ground-referenced) form. This demodulator design is an improvement over classic double-balanced demodulator designs using gain inversion, because it performs both demultiplexing and demodulation with one analog multiplexer.

The outputs from all 32 outputs (8 detector channels x 4 laser wavelengths) go to a 16 wide 2-to-1 analog multiplexer. The input selector for this mux comes from a five stage binary counter clocked by the “ADC convert” pacer clock output on the PC card.

A simplified block diagram depicting the Pulse-TDM concept.

A timing diagram for the NIRS-3 system. Each of the four sources is pulsed at a 12.5% duty cycle in rapid succession. The detector signal from each of the four sources is then synchronously demodulated to generate four analog voltages, each of which corresponds to the instantaneous flux reaching the detector from that source.

A block diagram of NIRS-3. A quartz crystal clock is divided down in frequency to drive both the laser pulsing circuitry and demodulation circuitry. The optical pulses from the lasers are converted to voltages by the silicon APD detector modules, which are then fed through variable-gain amplifiers and then demodulated to recover the slowly varying DC signals. The 32 analog signals are then digitized by an external PCMCIA-style ADC card. Both source selection and gain settings are computer-controlled through three digital input lines. Complementary clock lines protect against EMI-induced glitches during a measurement.

Mechanical Assembly Drawings

Analog Board Component Layout

Digital Board Component Layout

Back Panel Sketch

Front Panel sketch

Electrical Schematics

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